Jer Min Jou,: шукати на сайті Z-Library

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Пожертвування 15 вересня 2024 – 1 жовтня 2024

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Також БЕЗЛІМТНІ завантаження (протягом 31 дня після завершення пожертвування) доступні для ВСІХ користувачів, які підтримають проект в період збору коштів до 1 жовтня 2024.

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Serial diagnostic fault simulation for synchronous sequential circuits

Shung-Chih Chen, Jer Min Jou

Журнал:

Integration, the VLSI Journal

Рік:

1997

Мова:

english

Файл:

PDF, 1.01 MB

english, 1997

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme

Jer Min Jou,, Yeu-Horng Shiau,, Chin-Chi Liu,

Рік:

2001

Мова:

english

Файл:

PDF, 414 KB

english, 2001

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - A scalable pipelined architecture for separable 2-D discrete wavelet transform

Jer Min Jou,, Pei-Yin Chen,, Yeu-Horng Shiau,, Ming-Shiang Liang,

Рік:

1999

Мова:

english

Файл:

PDF, 367 KB

english, 1999

[IEEE IEEE TENCOM'02. 2002 IEEE Region 10 Conference on Computer, Communications, Control and Power Engineering - Beijing, China (28-31 Oct. 2002)] 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. - A low power implementation for the motion estimation processor

Jer Min Jou,, Yeu Horng Shiau,, Bu Ren Zheng,

Рік:

2002

Мова:

english

Файл:

PDF, 370 KB

english, 2002

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - A hierarchical interface design methodology and models for SoC IP integration

Jer-Min Jou,, Shiann-Rong Kuang,, Kuang-Ming Wu,

Рік:

2002

Мова:

english

Файл:

PDF, 335 KB

english, 2002

Adaptive arithmetic coding using fuzzy reasoning and grey prediction

Pei-Yin Chen, Jer Min Jou

Журнал:

Fuzzy Sets and Systems

Рік:

2000

Мова:

english

Файл:

PDF, 216 KB

english, 2000

A new 3-layer rectilinear area router with obstacle avoidance

Jer Min Jou, Jau Yien Lee

Журнал:

Integration, the VLSI Journal

Рік:

1989

Мова:

english

Файл:

PDF, 1.08 MB

english, 1989

A fast and efficient lossless data-compression method

Jer Min Jou, Pei-Yin Chen

Журнал:

IEEE Transactions on Communications

Рік:

1999

Мова:

english

Файл:

PDF, 120 KB

english, 1999

An efficient blocking-matching algorithm based on fuzzy reasoning

Pei-Yin Chen, Jer Min Jou

Журнал:

IEEE Transactions on Systems Man and Cybernetics Part B (Cybernetics)

Рік:

2001

Мова:

english

Файл:

PDF, 297 KB

english, 2001

Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis

Jer Min Jou, Yun-Lung Lee, Sih-Sian Wu

Журнал:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Рік:

2011

Мова:

english

Файл:

PDF, 589 KB

english, 2011

A Single Nucleotide Polymorphism Fine Mapping Study of Chromosome 1q42.1 Reveals the Vulnerability Genes for Schizophrenia, GNPAT and DISC1: Association with Impairment of Sustained Attention

Yu-Li Liu, Cathy Shen-Jang Fann, Chih-Min Liu, Wei J. Chen, Jer-Yuarn Wu, Shuen-Iu Hung, Chun-Houh Chen, Yuh-Shan Jou, Shih-Kai Liu, Tzung-Jeng Hwang, Ming H. Hsieh, Wen-Chen Ouyang, Hung-Yu Chan, Jia

Журнал:

Biological Psychiatry

Рік:

2006

Мова:

english

Файл:

PDF, 280 KB

english, 2006

RASD2, MYH9, and CACNG2 Genes at Chromosome 22q12 Associated with the Subgroup of Schizophrenia with Non-Deficit in Sustained Attention and Executive Function

Yu-Li Liu, Cathy Shen-Jang Fann, Chih-Min Liu, Wei J. Chen, Jer-Yuarn Wu, Shuen-Iu Hung, Chun-Houh Chen, Yuh-Shan Jou, Shi-Kai Liu, Tzung-Jeng Hwang, Ming H. Hsieh, Chien Ching Chang, Wei-Chih Yang, J

Журнал:

Biological Psychiatry

Рік:

2008

Мова:

english

Файл:

PDF, 148 KB

english, 2008

Diagnostic fault simulation for synchronous sequential circuits

Shung-Chih Chen, Jer Min Jou

Журнал:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Рік:

1997

Мова:

english

Файл:

PDF, 234 KB

english, 1997

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - A new pipelined architecture for fuzzy color correction

Jer Min Jou,, Shiann-Rang Kuang,, Yeu-Horng Shiau,

Рік:

1999

Мова:

english

Файл:

PDF, 380 KB

english, 1999

[IEEE ISCAS'95 - International Symposium on Circuits and Systems - Seattle, WA, USA (28 April-3 May 1995)] Proceedings of ISCAS'95 - International Symposium on Circuits and Systems - Distributed diagnostic fault simulation for synchronous sequential circuits by dynamic fault partitioning

Jer Min Jou,, Shung-Chih Chen,

Рік:

1995

Мова:

english

Файл:

PDF, 477 KB

english, 1995

[IEEE ISCAS '98 1998 IEEE International Symposium on Circuits and Systems - Monterey, CA, USA (31 May-3 June 1998)] ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) - Fast delay-dependent power estimation of large combinational circuits

Jer Min Jou,, Shung-Chih Chen,, Chih-Liang Wang,

Рік:

1998

Мова:

english

Файл:

PDF, 424 KB

english, 1998

[IEEE APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems - Taipei, Taiwan (5-8 Dec. 1994)] Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems - A new fault simulator for large synchronous sequential circuits

Jer Min Jou,, Shung-Chih Chen,

Рік:

1994

Мова:

english

Файл:

PDF, 765 KB

english, 1994

A low-cost Gray prediction search chip for motion estimation

Jer Min Jou,, Yeu-Horng Shiau,, Pei-Yin Chen,, Shiann-Rong Kuang,

Журнал:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Рік:

2002

Мова:

english

Файл:

PDF, 467 KB

english, 2002

[IEEE 2009 IEEE/ACS International Conference on Computer Systems and Applications - Rabat, Morocco (2009.05.10-2009.05.13)] 2009 IEEE/ACS International Conference on Computer Systems and Applications - A high-speed and decentralized arbiter design for NoC

Lee, Yun-Lung, Jou, Jer Min, Chen, Yen-Yu

Рік:

2009

Мова:

english

Файл:

PDF, 434 KB

english, 2009

[IEEE International Symposium on VLSI Technology Systems and Applications - Taipei, Taiwan (8-10 June 1999)] 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) - An efficient method for the decomposition and resynthesis of speed-independent circuits

Ren-Der Chen,, Jer-Min Jou,

Рік:

1999

Мова:

english

Файл:

PDF, 370 KB

english, 1999

STG-level decomposition and resynthesis of speed-independent circuits

Ren-Der Chen,, Jer-Min Jou,

Журнал:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Рік:

2002

Мова:

english

Файл:

PDF, 797 KB

english, 2002

[IEEE 1993 International Symposium on VLSI Technology, Systems, and Applications Technical Papers - Taipei, Taiwan (12-14 May 1993)] 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers - PARCRIPT: a very fast combinational fault simulator

Jer Min Jou,, Shung-Chih Chen,

Рік:

1993

Мова:

english

Файл:

PDF, 388 KB

english, 1993

[IEEE 2010 IEEE 8th Symposium on Application Specific Processors (SASP) - Anaheim, CA, USA (2010.06.13-2010.06.14)] 2010 IEEE 8th Symposium on Application Specific Processors (SASP) - Efficient design and generation of a multi-facet arbiter

Jer Min Jou,, Yun-Lung Lee,, Sih-Sian Wu,

Рік:

2010

Мова:

english

Файл:

PDF, 483 KB

english, 2010

The design of an adaptive on-line binary arithmetic-coding chip

Shiann-Rong Kuang,, Jer-Min Jou,, Yuh-Lin Chen,

Журнал:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Рік:

1998

Мова:

english

Файл:

PDF, 420 KB

english, 1998

[IEEE 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation - Taipei, Taiwan (20-22 Oct. 1999)] 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) - A gray-based block-matching algorithm and its VLSI architecture

Yeu-Horng Shiau,, Pei-Yin Chen,, Jer Min Jou,

Рік:

1999

Мова:

english

Файл:

PDF, 491 KB

english, 1999

[IEEE IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA (November 6-10, 1994)] IEEE/ACM International Conference on Computer-Aided Design - A Fast And Memory-efficient Diagnostic Fault Simulation For Sequential Circuits

Jer Min Jou,, Shung-Chih Chen,

Рік:

1984

Мова:

english

Файл:

PDF, 457 KB

english, 1984

A new efficient fuzzy algorithm for color correction

Jer Min Jou,, Shiann Rong Kuang,, Ren Der Chen,

Журнал:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Рік:

1999

Мова:

english

Файл:

PDF, 108 KB

english, 1999

[IEEE 2002 IEEE Asia-Pacific Conference on ASIC. - Taipei, Taiwan (6-8 Aug. 2002)] Proceedings. IEEE Asia-Pacific Conference on ASIC, - A novel motion estimation algorithm and its VLSI architecture

Jer Min Jou,, Yeu Horng Shiau,, Bu Ren Zheng,

Рік:

2002

Мова:

english

Файл:

PDF, 240 KB

english, 2002

An adaptive fuzzy logic controller: its VLSI architecture and applications

Jer Min Jou,, Pei-Yin Chen,, Sheng-Fu Yang,

Журнал:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Рік:

2000

Мова:

english

Файл:

PDF, 189 KB

english, 2000

[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Design of a distributed JPEG encoder on a scalable NoC platform

Lee, Yun-Lung, Yang, Jun-Wei, Jou, Jer Min

Рік:

2008

Мова:

english

Файл:

PDF, 223 KB

english, 2008

[IEEE 1993 International Symposium on VLSI Technology, Systems, and Applications Technical Papers - Taipei, Taiwan (12-14 May 1993)] 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers - Clique partitioning based integrated architecture synthesis for VLSI chips

Jer-Min Jou,, Shiann-Rong Kuang,, Ren-Der Chen,

Рік:

1993

Мова:

english

Файл:

PDF, 539 KB

english, 1993

Dynamic pipeline design of an adaptive binary arithmetic coder

Shiann Rong Kuang, Jer Min Jou, Ren Der Chen, Yeu Horng Shiau

Рік:

2001

Мова:

english

Файл:

PDF, 439 KB

english, 2001

[IEEE Comput. Soc. Press IEEE 3rd Asian Test Symposium (ATS) - Nara, Japan (15-17 Nov. 1994)] Proceedings of IEEE 3rd Asian Test Symposium (ATS) - Efficient diagnostic fault simulation for sequential circuits

Jer Min Jou,, Shung-Chih Chen,

Рік:

1994

Мова:

english

Файл:

PDF, 603 KB

english, 1994

[IEEE 1991., IEEE International Sympoisum on Circuits and Systems - Singapore (11-14 June 1991)] 1991., IEEE International Sympoisum on Circuits and Systems - PASS: a package for automatic scheduling and sharing pipelined data paths

Jer Min Jou,, Chengli Cin Chin,, Yi Ru Li,

Рік:

1991

Мова:

english

Файл:

PDF, 497 KB

english, 1991

An efficient VLSI switch-box router

Jer Min Jou,, Jau Yien Lee,, Yachyang Sun,, Jhing Fa Wang,

Журнал:

IEEE Design & Test of Computers

Рік:

1990

Мова:

english

Файл:

PDF, 935 KB

english, 1990

[IEEE 2006 IEEE Asian Solid-State Circuits Conference - Hangzhou, China (2006.11.13-2006.11.15)] 2006 IEEE Asian Solid-State Circuits Conference - Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs

Hsu, Shih-Hsun, Lin, Yu-Xuan, Jou, Jer-Min

Рік:

2006

Мова:

english

Файл:

PDF, 5.12 MB

english, 2006

The gray prediction search algorithm for block motion estimation

Jer Min Jou,, Pei-Yin Chen,, Jian-Ming Sun,

Журнал:

IEEE Transactions on Circuits and Systems for Video Technology

Рік:

1999

Мова:

english

Файл:

PDF, 262 KB

english, 1999

[IEEE IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) - Porto Alegre, Brazil (2007.03.9-2007.03.11)] IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) - A Novel Reconfigurable Computation Unit for DSP Applications

Jou, Jer Min, Lee, Yun-Lung, Lin, Chen-Yen, Sun, Chien-Ming

Рік:

2007

Мова:

english

Файл:

PDF, 543 KB

english, 2007

[IEEE 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 - Atlanta, GA, USA (12-15 May 1996)] 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 - An on line adaptive data compression chip using arithmetic codes

Jer-Min Jou,, Shiann-Rong Kuang,, Yuh-Lin Chen,, Chung-Yuan Chiang,

Рік:

1996

Мова:

english

Файл:

PDF, 471 KB

english, 1996

Design of low-error fixed-width multiplier for DSP applications

Jou, Jer Min, Kuang, Shiann Rong

Журнал:

Electronics Letters

Рік:

1997

Мова:

english

Файл:

PDF, 314 KB

english, 1997

[IEEE 1995 IEEE International Conference on Fuzzy Systems. The International Joint Conference of the Fourth IEEE International Conference on Fuzzy Systems and The Second International Fuzzy Engineering Symposium - Yokohama, Japan (20-24 March 1995)] Proceedings of 1995 IEEE International Conference on Fuzzy Systems. The International Joint Conference of the Fourth IEEE International Conference on Fuzzy Systems and The Second International Fuzzy Engineering Symposium - Design and implementation of a self-adaptive fuzzy inference engine

Jer Min Jou,, Pei-Yin Chen,, Sheng-Fu Yang,

Рік:

1995

Мова:

english

Файл:

PDF, 509 KB

english, 1995

[IEEE ICECS'99. 6th IEEE International Conference on Electronics, Circuits and Systems - Pafos, Cyprus (5-8 Sept. 1999)] ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) - A grey prediction motion estimator for digital image processing

Jer Min Jou,, Pei-Yin Chen,, Yeu-Horng Shiau,, Jian-Ming Sun,

Рік:

1999

Мова:

english

Файл:

PDF, 384 KB

english, 1999

[IEEE ICECS'99. 6th IEEE International Conference on Electronics, Circuits and Systems - Pafos, Cyprus (5-8 Sept. 1999)] ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) - An efficient method for the decomposition and resynthesis of speed-independent circuits

Ren-Der Chen,, Jer Min Jou,, Yeu-Horng Shiau,

Рік:

1999

Файл:

PDF, 317 KB

1999

[IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 - Multiport memory based data path allocation focusing on interconnection optimization

Jer-Min Jou,, Ren-Der Chen,, Shiann-Rong Kuang,

Рік:

1994

Файл:

PDF, 486 KB

1994

[IEEE ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems - Malta (2-5 Sept. 2001)] ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) - An efficient VLSI architecture for HMM-based speech recognition

Jer Min Jou,, Yeu-Horng Shiau,, Chen-Jen Huang,

Рік:

2001

Мова:

english

Файл:

PDF, 423 KB

english, 2001

[IEEE ICECS'99. 6th IEEE International Conference on Electronics, Circuits and Systems - Pafos, Cyprus (5-8 Sept. 1999)] ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) - An efficient method for the decomposition and resynthesis of speed-independent circuits

Ren-Der Chen,, Jer Min Jou,, Yeu-Horng Shiau,

Рік:

1999

Мова:

english

Файл:

PDF, 317 KB

english, 1999

[IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 - Multiport memory based data path allocation focusing on interconnection optimization

Jer-Min Jou,, Ren-Der Chen,, Shiann-Rong Kuang,

Рік:

1994

Мова:

english

Файл:

PDF, 486 KB

english, 1994

[IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 - A super fast and memory efficient diagnostic simulation algorithm for combinational circuits

Jer Min Jou,, Shung-Chih Chen,, Ren-Der Chen,

Рік:

1994

Мова:

english

Файл:

PDF, 365 KB

english, 1994

[IEEE ISCAS '98 1998 IEEE International Symposium on Circuits and Systems - Monterey, CA, USA (31 May-3 June 1998)] ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) - An adaptive arithmetic coding method using fuzzy logic and Gray theory

Jer Min Jou,, Pei-Yin Chen,

Рік:

1998

Мова:

english

Файл:

PDF, 376 KB

english, 1998